1. Field of the Invention
The present invention relates generally to semiconductor devices. More particularly, the present invention relates to phase locked loop (PLL) implementations for semiconductor devices.
2. Background Art
Phase locked loops (PLLs) are used throughout the electronic device industry in a variety of circumstances, from tuning radio receivers to a particular frequency band to generating precise synthesized tones for musical equipment. In particular, PLLs may be used to clean and propagate a clock signal or a multiple of a clock signal throughout a computational device.
Typically, PLLs accept a provided reference signal and “lock” to the frequency and phase of the provided reference signal after a settling period, where the feedback loop of the PLL incrementally adjusts an operating frequency of the PLL until a PLL feedback signal matches the reference signal's frequency and phase. The stability of a particular PLL depends on its ability to lock to a particular reference signal frequency, and so depends on the loop bandwidth and damping factor of the PLL, where too little or too much bandwidth or too long a settling period may lead to unstable operation. For example, a PLL's loop bandwidth should be sufficiently large to reduce input tracking jitter and to allow for lock to a wide range of reference signal frequencies, but too large a loop bandwidth allows off-frequency noise to encroach into the operation of the PLL, which introduces errors into the operating frequency of the PLL. Similarly, a damping factor that varies with operating frequency can introduce errors into the operating frequency of the PLL that limits its utility to a relatively narrow operating frequency range. Because contemporary PLLs are often required to lock to relatively wide ranges of reference signal frequencies, bandwidth and damping related PLL operating frequency errors have become a significant problem.
Conventional methods to address these problems include adaptive bandwidth loop filter implementations, where loop bandwidth follows operating frequency so as to limit input noise without necessarily limiting an operating frequency range, and where a damping factor is kept reasonably constant over a selected operating frequency range, but these implementations are typically complex and require a relatively large amount of die space to fabricate. Furthermore, these implementations also typically introduce or at least do not fully address other sources of errors in an operating frequency of a PLL, such as decreased jitter performance due to supply or common mode noise and substrate noise.
Accordingly, there is a need to overcome the drawbacks and deficiencies in the art by providing a compact PLL implementation with an increased jitter performance and increased operating frequency range.